DDS and PLL Jammer Device

In the technical fields of modern electronic measurement, radar, communication systems, electronic countermeasures, etc., a signal source with a wide frequency range, high resolution, and fast conversion of multiple modes is important and indispensable. With the rapid development of electronic technology and integrated circuits,  large-scale DDS chips with high-frequency resolution (MHz level) and fast frequency conversion (μs to ns level) appeared. The upper limit of the frequency of the output signal is basically within the HF or VHF frequency band, which is lower than the signal frequency obtained by PLL synthesis technology and direct analog synthesis technology. When it is required to obtain ultra-high frequency (UHF) or even microwave signals with high-frequency resolution, fast conversion speed, and low noise, DDS+PLL technology shows strong vitality.

DDS: Direct Digital Synthesizer. It is actually a frequency divider: it divides the system clock by programming the frequency control word to generate the required frequency. DDS has two outstanding features. On the one hand, DDS works in the digital domain. Once the frequency control word is updated, the output frequency changes accordingly, and its frequency hopping rate is high. On the other hand, due to the wide width of the frequency control word (48bit or higher), the frequency resolution is high.

PLL (Phase Locked Loop): A phase-locked loop or phase-locked loop, which is used to unify and integrate clock signals to enable high-frequency devices to work normally, such as accessing data in memory. PLL is used for feedback technology in oscillators. For many electronic devices to work properly, they usually need the external input signal to be synchronized with the internal oscillation signal. Due to process and cost reasons, ordinary crystal oscillators cannot achieve very high frequencies. When high-frequency applications are required, the corresponding device VCO is used to convert high frequencies, but it is not stable. Therefore, a stable and high-frequency clock signal can be achieved by using a phase-locked loop.

1. The upper limit of DDS output frequency depends on the reference clock, and can only reach half of the reference due to ADC conversion. The upper limit of PLL output frequency depends on the upper limit of VCO.
2. DDS frequency switching is implemented in the digital domain, and the time is very fast, which can reach the nanosecond level; PLL locking time depends on the hardware time, which is at the microsecond level;
3. DDS does not require additional analog devices, so the power consumption is low. Since the frequency of the PLLis all implemented in analog devices, the power consumption is relatively high.

ZDTECH newly developed dual digital modules device for customers to better jammer drone equipment. Because many drone equipments are now customized and have special channels, we use DDS+PLL equipment for better results.